FULL ADDER GATE LEVEL MODEL
module favj(a,b,c,sum,carry); output sum,carry; input a,b,c; wire w1,w2,w3; xor x1(sum,a,b,c); and a1(w1,a,b); and a2(w2,b,c); and a3(w3,c,a); or o1(carry,w1,w2,w3); endmodule
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