NOT GATE USING CMOS module not1(out,in); output out; input in; supply1 vdd; supply0 gnd; pmos p1(out,vdd,in); nmos n1(out,gnd,in);
endmodule
http://verilogbyvijaysn.blogspot.in/2015/07/cmos-circuits-not-gate-using-cmos.html
http://verilogbyvijaysn.blogspot.in/2015/07/cmos-circuits-not-gate-using-cmos.html
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