4 BIT PRBS GENERATOR TEST BENCH
PRBS GENERATOR
module prbs4bit2(q,clk);
output [3:0]q;
input clk;
reg [3:0]q;
initial
q<=4'b1;
always @(posedge clk)
begin
q={q[2:0],q[2]^q[1]};
end
endmodule
TEST BENCH
module prbstest;
reg clk;
wire [3:0]q;
prbs4bit2 p1(q,clk);
initial
clk=1;
always #10 clk=~clk;
endmodule
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