Shift register

Serial in serial out

// File : Design of Serial In -
Serial Out Shift Register using d_flip
flop.v
module siso ( din ,clk ,reset ,dout );
output dout ;
input din ;
input clk ;
input reset ;
wire [2:0]s;
d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));
d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));
d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));
d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout));
endmodule
// -------------- D flip flop design -
-----------------------
//------------------------------
--------------------------------
---------------
//
// Title : d_flip_flop
// Design : upload_design1
// Author : Naresh Singh Dobal
// Company : nsd
//
//------------------------------
--------------------------------
---------------
//
// File : d_flip_flop.v
module d_flip_flop ( din ,clk ,reset
,dout );
output dout ;
reg dout;
input din ;
input clk ;
input reset ;
always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end
endmodule

Serial in parallel out

// File : Serial IN Parallel OUT
Shift Register using Behavior
Modeling Style.v
module SIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assign dout = s;
endmodule

Parallel in parallel out

// File : parallel IN - Parallel
OUT Shift Register using Behavior
Modeling Style.v
module PIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din;
end
endmodule

Parallel in serial out

// File : Parallel IN - Serial OUT
Shift Register.v
module parallel_in_serial_out ( din
,clk ,reset ,load ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end
end
endmodule

CMOS circuits- NOT gate using Cmos

NOT GATE USING CMOS
module not1(out,in);
output out;
input in;
supply1 vdd;
supply0 gnd;
pmos p1(out,vdd,in);
nmos n1(out,gnd,in);

endmodule

CMOS circuits- NOR gate using Cmos

NOR SWITCH USING CMOS
module switchnor(out,a,b);
output out;
input a,b;
supply1 pwr;
supply0 gnd;
wire w1;
pmos (w1,a,pwr);
pmos (out,b,w1);
nmos (out,a,gnd);
nmos (out,b,gnd);
endmodule

CMOS circuits- NAND gate using cmos

NAND GATE USING CMOS

module nand3ip(out,a,b,c);
output out;
input a,b,c

supply1 vcc;
supply0 gnd;

wire w1,w2;

pmos p1(out,a,vcc);
pmos p2(out,b,vcc);
pmos p3(out,c,vcc);

nmos n1(out,a,w1);
nmos n2(out,b,w2);
nmos n3(out,c,gnd);
endmodule

Counters- MOD12 Up counter

MOD 12 UP COUNTER
module mod12upcounter(out,rst,clk);
output [3:0]out;
input rst,clk;
reg [3:0]out;
always @(posedge clk)
begin
if(rst|out==4'b1011)
out<=4'b0000;
else
out<=out+1;
end
endmodule

Counters- MOD10 Up counter

MOD 10 UP COUNTER
module mod10bit2(out,rst,clk);
output [3:0]out;
input clk,rst;
reg [3:0]out;
always @(posedge clk)
begin
if(rst|out==4'b1001)
out<=4'b0000;
else
out<=out+1;
end
endmodule

Counters- Ring counter

RING COUNTER USING D FLIP FLOP

D FLIP FLOP
module df1(q,d,c);
output q;
input d,c;
reg q;
initial
q=1'b1;
always@(posedge c)
q=d;
endmodule

RING COUNTER
module ringcounter(q,clk);
inout [3:0]q;
input clk;
df1 f1(q[0],q[3],clk);
df2 f2(q[1],q[0],clk);
df2 f3(q[2],q[1],clk);
df2 f4(q[3],q[2],clk);
endmodule