Shift register

Serial in serial out

// File : Design of Serial In -
Serial Out Shift Register using d_flip
flop.v
module siso ( din ,clk ,reset ,dout );
output dout ;
input din ;
input clk ;
input reset ;
wire [2:0]s;
d_flip_flop u0 (.din(din),
.clk(clk),
.reset(reset),
.dout(s[0]));
d_flip_flop u1 (.din(s[0]),
.clk(clk),
.reset(reset),
.dout(s[1]));
d_flip_flop u2 (.din(s[1]),
.clk(clk),
.reset(reset),
.dout(s[2]));
d_flip_flop u3 (.din(s[2]),
.clk(clk),
.reset(reset),
.dout(dout));
endmodule
// -------------- D flip flop design -
-----------------------
//------------------------------
--------------------------------
---------------
//
// Title : d_flip_flop
// Design : upload_design1
// Author : Naresh Singh Dobal
// Company : nsd
//
//------------------------------
--------------------------------
---------------
//
// File : d_flip_flop.v
module d_flip_flop ( din ,clk ,reset
,dout );
output dout ;
reg dout;
input din ;
input clk ;
input reset ;
always @ (posedge clk)
begin
if (reset)
dout <= 1;
else
dout <= din;
end
endmodule

Serial in parallel out

// File : Serial IN Parallel OUT
Shift Register using Behavior
Modeling Style.v
module SIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assign dout = s;
endmodule

Parallel in parallel out

// File : parallel IN - Parallel
OUT Shift Register using Behavior
Modeling Style.v
module PIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
reg [3:0] dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= din;
end
endmodule

Parallel in serial out

// File : Parallel IN - Serial OUT
Shift Register.v
module parallel_in_serial_out ( din
,clk ,reset ,load ,dout );
output dout ;
reg dout ;
input [3:0] din ;
wire [3:0] din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
input load ;
wire load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp <= 1;
else if (load)
temp <= din;
else begin
dout <= temp[3];
temp <= {temp[2:0],1'b0};
end
end
endmodule

CMOS circuits- NOT gate using Cmos

NOT GATE USING CMOS
module not1(out,in);
output out;
input in;
supply1 vdd;
supply0 gnd;
pmos p1(out,vdd,in);
nmos n1(out,gnd,in);

endmodule

CMOS circuits- NOR gate using Cmos

NOR SWITCH USING CMOS
module switchnor(out,a,b);
output out;
input a,b;
supply1 pwr;
supply0 gnd;
wire w1;
pmos (w1,a,pwr);
pmos (out,b,w1);
nmos (out,a,gnd);
nmos (out,b,gnd);
endmodule

CMOS circuits- NAND gate using cmos

NAND GATE USING CMOS

module nand3ip(out,a,b,c);
output out;
input a,b,c

supply1 vcc;
supply0 gnd;

wire w1,w2;

pmos p1(out,a,vcc);
pmos p2(out,b,vcc);
pmos p3(out,c,vcc);

nmos n1(out,a,w1);
nmos n2(out,b,w2);
nmos n3(out,c,gnd);
endmodule

Counters- MOD12 Up counter

MOD 12 UP COUNTER
module mod12upcounter(out,rst,clk);
output [3:0]out;
input rst,clk;
reg [3:0]out;
always @(posedge clk)
begin
if(rst|out==4'b1011)
out<=4'b0000;
else
out<=out+1;
end
endmodule

Counters- MOD10 Up counter

MOD 10 UP COUNTER
module mod10bit2(out,rst,clk);
output [3:0]out;
input clk,rst;
reg [3:0]out;
always @(posedge clk)
begin
if(rst|out==4'b1001)
out<=4'b0000;
else
out<=out+1;
end
endmodule

Counters- Ring counter

RING COUNTER USING D FLIP FLOP

D FLIP FLOP
module df1(q,d,c);
output q;
input d,c;
reg q;
initial
q=1'b1;
always@(posedge c)
q=d;
endmodule

RING COUNTER
module ringcounter(q,clk);
inout [3:0]q;
input clk;
df1 f1(q[0],q[3],clk);
df2 f2(q[1],q[0],clk);
df2 f3(q[2],q[1],clk);
df2 f4(q[3],q[2],clk);
endmodule

Counters- Johnson Counter

JOHNSON COUNTER USING D FLIP FLOP

D FLIP FLOP
module df1(q,d,c);
output q;
input d,c;
reg q;
initial
q=1'b1;
always@(posedge c)
q=d;
endmodule

JOHNSON COUNTER
module johnsoncounter(q,clk);
inout [3:0]q;
input clk;
wire w;
not(w,q[3]);
df1 f1(q[0],w,clk);
df2 f2(q[1],q[0],clk);
df2 f3(q[2],q[1],clk);
df2 f4(q[3],q[2],clk);

endmodule

Counters- Decade counter

DECADE COUNTER
module decadecounter(q,clk,reset);
output [3:0]q;
input clk,reset;
reg [3:0]q;
always @(posedge clk)
begin
if(reset|q<=4'b0000)
q<=4'b1111;
else
q<=q-1;
end

endmodule

Counters- Updown counter 4bit testbench

4 BIT UPDOWN COUNTER TESTBENCH
UP DOWN COUNTER
module updowncounter(q,clk,rst,up);
output [3:0]q;
input clk,rst,up;
reg [3:0]q;
always @(posedge clk)
begin

if(up==1)
begin
if(rst|q==4'b1111)
q<=4'b0000;
else
q<=q+4'b1;
end
else
begin
if(rst|q==4'b0000)
q<=4'b1111;
else
q<=q-1;
end

end

endmodule

TEST BENCH
module updowntest;
reg clk,rst,up;
wire [3:0]q;
updowncounter c1(q,clk,rst,up);
initial
begin
rst=1;
up=0;
clk=1;
end
always #5 clk=~clk;
always #80 rst=~rst;
always #160 up=~up;

endmodule

Flipflops and Latches- T Flipflop testbench

T FLIPFLOP TEST BENCH
T FLIPFLOP
module tff(q,clk,d,t);
output q;
input clk,d,t;
reg q;
initial
q=0;
always @(posedge clk)
begin
if(t)
q<=~d;
else
q<=d;
end
endmodule

TEST BENCH
module tfftest;
reg d,clk,t;
wire q;
tff t2(q,clk,d,t);
initial
begin
clk=0;
d=0;
t=0;
end
always #50 clk=~clk;
always #100 d=~d;
always #200 t=~t;

endmodule

Flipflops and Latches- D Flipflop testbench

D FLIPFLOP TEST BENCH
D FLIPFLOP
module dff(q,clk,d);
output q;
input clk,d;
reg q;
initial
q<=0;
always @(posedge clk)
begin
q<=d;
end
endmodule

TEST BENCH
module dfftest1;
reg clk,d;
wire q;
dff f1(q,clk,d);
initial
begin
clk=0;
d=0;
end
always #75 clk=~clk;
always #150 d=~d;
endmodule

Flipflops and Latches- D Flipflop

D FLIP FLOP

module dff(q,d,clk,reset);
input d,clk,reset;
output q;
reg q;
always @(posedge clk)
begin
if(~reset) q<=1'b0;
else q<=d;
end
endmodule

Flipflops and Latches- SR Latch

SR LATCH
module SR_latch_gate (input R, input S, output Q, output Qbar);
nor (Q, R, Qbar);
nor (Qbar, S, Q);
endmodule

Flipflops and Latches- D Latch

D LATCH

module dlatch(q,d,r);
input d,r;
output q;
reg q;
always @(d or r)
begin
if(r) q<=d;
else q<=~d;
end
endmodule

Combinational circuits- Magnitude comparator 4bit

4 BIT MAGNITUDE COMPARATOR

module magn4bitcomp(equal,lower,higher,a,b);
output equal,lower,higher;
reg equal,lower,higher;
input [3:0]a;
input [3:0]b;
always @(a or b)
begin
if (a>b) begin
equal=0;
higher=1;
lower=0;
end else if(a==b) begin
equal=1;
higher=0;
lower=0;
end else begin
equal=0;
lower=1;
higher=0;
end
end

endmodule

Combinational circuits- Prbs generator 4bit

4 BIT PRBS GENERATOR
module prbs4bit(q,rst,clk,en);
output [3:0]q;
input rst,clk,en;
reg [3:0]q;
always @(posedge clk)
begin
if(rst)
q<=4'd1;
else if(en);
q<={q[2:0],q[2]^q[1]};
end
endmodule

Combinational circuits-prbs generator 4bit testbench

4 BIT PRBS GENERATOR TEST BENCH
PRBS GENERATOR
module prbs4bit2(q,clk);
output [3:0]q;
input clk;
reg [3:0]q;
initial
q<=4'b1;
always @(posedge clk)
begin
q={q[2:0],q[2]^q[1]};
end
endmodule

TEST BENCH
module prbstest;
reg clk;
wire [3:0]q;
prbs4bit2 p1(q,clk);
initial
clk=1;
always #10 clk=~clk;
endmodule

Combinational circuits-Prbs generator 3bit

3 BIT PRBS GENERATOR
module prbs3bit(q,clk,rst);
output [2:0]q;
input clk,rst;
reg [2:0]q;
always @(posedge clk)
begin
if(rst)
q<=3'b1;
else
q<={q[1:0],q[2]^q[1]};
end
endmodule

Combinational circuits-Test bench

DECODER TEST BENCH PROGRAM

DECODER 3 OUT OF 8
module decode3to8(out,in);
output [7:0]out;
input [2:0]in;
reg [7:0]out;
always @(in)
begin
case(in)
3'b000:out=8'b10000000;
3'b001:out=8'b01000000;
3'b010:out=8'b00100000;
3'b011:out=8'b00010000;
3'b100:out=8'b00001000;
3'b101:out=8'b00000100;
3'b110:out=8'b00000010;
3'b111:out=8'b00000001;
endcase
end

endmodule

TEST BENCH
module decodetest;
reg [2:0]in;
wire [7:0]out;
decode3to8 d1(out,in);
initial
begin
in=3'b000;
#75 in=3'b001;
#75 in=3'b010;
#75 in=3'b011;
#75 in=3'b100;
#75 in=3'b101;
#75 in=3'b110;
#75 in=3'b111;
end
endmodule

Combinational circuits-Decoder 3of8

DECODER 3 out of 8

module decoder3outof8(d,in);
output [7:0]d;
input [2:0]in;
reg [7:0]d;
always @(in)
begin
case(in)
3'b000:d=8'b10000000;
3'b001:d=8'b01000000;
3'b010:d=8'b00100000;
3'b011:d=8'b00010000;
3'b100:d=8'b00001000;
3'b101:d=8'b00000100;
3'b110:d=8'b00000010;
3'b111:d=8'b00000001;
endcase
end
endmodule

Combinational circuits- 2of4 Decoder

2 OUT OF 4 DECODER
module decoder2of4(out,in);
output[3:0]out;
input [1:0]in;
reg [3:0]out;
always @(in)
begin
case(in)
2'b00:out=4'b1000;
2'b01:out=4'b0100;
2'b10:out=4'b0010;
2'b11:out=4'b0001;
endcase
end
endmodule

Combinational circuits-Demux1of8 testbench

DEMUX 1 OF 8 TEST BENCH
DEMUX
module demux1of8(d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0,d);
output d0,d1,d2,d3,d4,d5,d6,d7;
input s2,s1,s0,d;
wire w2,w1,w0;
not n1(w2,s2);
not n2(w1,s1);
not n3(w0,s0);
and a1(d0,w2,w1,w0,d);
and a2(d1,w2,w1,s0,d);
and a3(d2,w2,s1,w0,d);
and a4(d3,w2,s1,s0,d);
and a5(d4,s2,w1,w0,d);
and a6(d5,s2,w1,s0,d);
and a7(d6,s2,s1,w0,d);
and a8(d7,s2,s1,s0,d);

endmodule

TEST BENCH
module test;
reg d;
reg s2,s1,s0;
wire d0,d1,d2,d3,d4,d5,d6,d7;
demux1of8 h1(d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0,d);
initial
begin
d=1;
s2=0;s1=0;s0=0;
d=1;
#75 s2=0;s1=0;s0=1;
d=1;
#75 s2=0;s1=1;s0=0;
d=1;
#75 s2=0;s1=1;s0=1;
d=1;
#75 s2=1;s1=0;s0=0;
d=1;
#75 s2=1;s1=0;s0=1;
d=1;
#75 s2=1;s1=1;s0=0;
d=1;
#75 s2=1;s1=1;s0=1;
end
endmodule

Combinational.circuits- Demux1of4

DEMUX 1 OF 4

module demux1of4(a,b,c,d,data,s1,s0);
output a,b,c,d;
input data;
input s1,s0;
assign a=(data&~s1&~s0);
assign b=(data&~s1&s0);
assign c=(data&s1&~s0);
assign d=(data&s1&s0);
endmodule

Combinational circuits- Mux8to1 by mux2to1 and testbench

MUX 8 TO 1 USING MUX2TO1 AND ITS TESTBENCH

MUX 2 TO 1
module mux2to1(out,s,a,b);
output out;
input s,a,b;
wire w1,w2,w3;
not n1(w1,s);
and a1(w2,w1,a);
and a2(w3,s,b);
or o1(out,w2,w3);
endmodule

MUX 4 TO 1
module mux4(out,s1,s0,a,b,c,d);
output out;
input s1,s0;
input a,b,c,d;
wire w1,w2;
mux2to1 m1(w1,s0,a,b);
mux2to1 m2(w2,s0,c,d);
mux2to1 m3(out,s1,w1,w2);

endmodule

MUX 8 TO 1
module mux8(out,s2,s1,s0,a,b,c,d,e,f,g,h);
output out;
input s2,s1,s0;
input a,b,c,d,e,f,g,h;
wire w1,w2;
mux4 m1(w1,s1,s0,a,b,c,d);
mux4 m2(w2,s1,s0,e,f,g,h);
mux2to1 m3(out,s2,w1,w2);
endmodule

MUX 8 TO 1 TEST BENCH
module mux8tst;
reg a,b,c,d,e,f,g,h;
reg s2,s1,s0;
wire out;;
mux8 m1(out,s2,s1,s0,a,b,c,d,e,f,g,h);
initial
begin
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
s2=0;s1=0;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=0;s1=0;s0=1;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=0;s1=1;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=0;s1=1;s0=1;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=0;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=0;s0=1;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=1;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=1;s0=1;
end

endmodule

Combinational circuits- Mux4to1 using Mux2:1 and testbench

MUX 4 TO 1 USING MUX 2 TO 1 AND ITS TESTBENCH

MUX 2 TO 1
module mux2to1(out,s,a,b);
output out;
input s,a,b;
wire w1,w2,w3;
not n1(w1,s);
and a1(w2,w1,a);
and a2(w3,s,b);
or o1(out,w2,w3);
endmodule

MUX 4 TO 1
module mux4(out,s1,s0,a,b,c,d);
output out;
input s1,s0;
input a,b,c,d;
wire w1,w2;
mux2to1 m1(w1,s0,a,b);
mux2to1 m2(w2,s0,c,d);
mux2to1 m3(out,s1,w1,w2);

endmodule

TEST BENCH
module muxtest;
reg a,b,c,d,s1,s0;
wire out;
mux4 m1(out,s1,s0,a,b,c,d);
initial
begin
a=1;b=0;c=1;d=0;
s1=0;s0=0;
a=1;b=0;c=1;d=0;
#75 s1=0;s0=1;
a=1;b=0;c=1;d=0;
#75 s1=1;s0=0;
a=1;b=0;c=1;d=0;
#75 s1=1;s0=1;
end
endmodule

Arithmetic circuits- 4bit multiplier

4 BIT MULTIPLIER
module multiplie4bit(out,a,b);
output [7:0]out;
input [3:0]a,b;
assign out=a*b;
endmodule

Arithmetic circuits- 2 bit Multiplier

2 BIT MULTIPLIER
module multiplier2bit(out,a,b);
output [3:0]out;
input [1:0]a;
input [1:0]b;
assign out=a*b;
endmodule

Arithmetic circuits- 8bit Accumulator Testbench

8 BIT ACCUMULATOR TEST BENCH

8 BIT ACCUMULATOR
module acc8bit(out,clk,in);
output [7:0]out;
input [7:0]in;
input clk;
reg [7:0]out;
initial
out=8'b0;
always @(posedge clk)
begin
out<=out+in;
end
endmodule

ACCUMULATOR TEST BENCH
module acctest;
reg clk;
reg [7:0]in;
wire [7:0]out;
acc8bit a1(out,clk,in);
initial
begin
clk=1;
in=8'b00000001;
end
always #10 clk=~clk;

endmodule

Arithmetic circuits- 8bit adder

8 BIT ADDER

module adder8bit1(carry,sum,a,b,ci);
output carry;
output [7:0]sum;
input [7:0]a,b;
input ci;
reg [7:0]sum;
reg carry;
reg [8:0]tmp;
always @(a,b,ci)
begin
assign tmp=a+b+ci;
assign sum=tmp[7:0];
assign carry=tmp[8];
end
endmodule

Arithmetic circuits- 4bit adder

4 BIT ADDER

module adder4bit(carry,sum,a,b);
output [3:0]sum;
output carry ;
input [3:0]a,b;
reg [3:0]sum;
reg carry;
reg [4:0]tmp;
always @(a,b)
begin
assign tmp=a+b;
assign sum=tmp[3:0];
assign carry=tmp[4];
end
endmodule

Arithmetic circuits- Ripple carry adder test bench

4 BIT RIPPLE CARRY ADDER TEST BENCH
FULL ADDER
module faa(carry,sum,a,b,c);
output carry,sum;
input a,b,c;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

4 BIT RIPPLE CARRY ADDER
module ripple4bit(s,carry,a,b,cin);
output [3:0]s;
output carry;
input [3:0]a,b;
input cin;
wire c1,c2,c3;
faa f1(c1,s[0],a[0],b[0],cin);
faa f2(c2,s[1],a[1],b[1],c1);
faa f3(c3,s[2],a[2],b[2],c2);
faa f4(carry,s[3],a[3],b[3],c3);
endmodule

TEST BENCH
module rippletet4bit;
reg [3:0]a,b;
reg c;
wire [3:0]sum;
wire carry;
ripple4bit r1(sum,carry,a,b,c);
initial
begin

a=0000;b=0000;c=0;
#100 a=0001;b=0001;c=0;
#100 a=0010;b=0010;c=0;
#100 a=0100;b=0100;c=0;
#100 a=0101;b=0101;c=0;
#100 a=0110;b=0110;c=0;
#100 a=0111;b=0111;c=0;
#100 a=1000;b=1000;c=0;
#100 a=1001;b=1001;c=0;
#100 a=1010;b=1010;c=0;
#100 a=1011;b=1011;c=0;
#100 a=1100;b=1100;c=0;
#100 a=1101;b=1101;c=0;
#100 a=1110;b=1110;c=0;
#100 a=1111;b=1111;c=0;
#100 a=0000;b=0000;c=1;
#100 a=0001;b=0001;c=1;
#100 a=0010;b=0010;c=1;
#100 a=0100;b=0100;c=1;
#100 a=0101;b=0101;c=1;
#100 a=0110;b=0110;c=1;
#100 a=0111;b=0111;c=1;
#100 a=1000;b=1000;c=1;
#100 a=1001;b=1001;c=1;
#100 a=1010;b=1010;c=1;
#100 a=1011;b=1011;c=1;
#100 a=1100;b=1100;c=1;
#100 a=1101;b=1101;c=1;
#100 a=1110;b=1110;c=1;
#100 a=1111;b=1111;c=1;

end
endmodule

Arithmetic circuits- 8bit Ripple carry adder

8 BIT RIPPLE CARRY ADDER USING FULL ADDER
FULL ADDER
module faa(carry,sum,a,b,c);
output carry,sum;
input a,b,c;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

RIPPLE CARRY ADDER
module ripple8bit(carry,s,a,b,cin);
output carry;
output [7:0]s;
input [7:0]a,b;
input cin;
wire c1,c2,c3,c4,c5,c6,c7;
faa f1(c1,s[0],a[0],b[0],cin);
faa f2(c2,s[1],a[1],b[1],c1);
faa f3(c3,s[2],a[2],b[2],c2);
faa f4(c4,s[3],a[3],b[3],c3);
faa f5(c5,s[4],a[4],b[4],c4);
faa f6(c6,s[5],a[5],b[5],c5);
faa f7(c7,s[6],a[6],b[6],c6);
faa f8(carry,s[7],a[7],b[7],c7);
endmodule

Arithmetic circuits- Ripple carry adder using full adder

RIPPLE CARRY ADDER USING FULL ADDER

HALF ADDER
module havj(sum,carry,a,b);
output sum,carry;
input a,b;
xor x1(sum,a,b);
and a1(carry,a,b);
endmodule

FULL ADDER USING HALF ADDER
module favj(sum,carry,a,b,c);
output sum,carry;
input a,b,c;
wire w1,c1,c2;
havj v1(w1,c1,a,b);
havj v2(sum,c2,c,w1);
or o1(carry,c1,c2);
endmodule
RIPPLE CARRY ADDER
module ripplevj(carry,sum,a,b,cin);
output carry;
output [3:0]sum;
input [3:0]a;
input [3:0]b;
input cin;
wire c1,c2,c3;
favj a1(sum[0],c1,a[0],b[0],cin);
favj a2(sum[1],c2,a[1],b[1],c1);
favj a3(sum[2],c3,a[2],b[2],c2);
favj a4(sum[3],carry,a[3],b[3],c3);
endmodule

Arithmetic circuits- Full subtractor using gates

FULL SUBTRACTOR GATE LEVEL MODEL

module fsvj(borrow,diff,a,b,c);
output borrow,diff;
input a,b,c;
wire w1,w2,w3,w4,w5,w6,w7;
xor (diff,a,b,c);
not n1(w1,a);
not n2(w2,b);
not n3(w3,c);
and a1(w4,a,b,c);
and a2(w5,w1,b,c);
and a3(w6,w1,w2,c);
and a4(w7,w1,b,c);
or o1(borrow,w4,w5,w6,w7);
endmodule

Arithmetic circuits- Full adder test bench

FULL ADDER TEST BENCH

FULL ADDER
module faa(carry,sum,a,b,c);
output carry,sum;
input a,b,c;
assign sum=a^b^c;
assign carry=(a&b)|(b&c)|(c&a);
endmodule

TEST BENCH
module ftest;
reg a;
reg b;
reg c;
wire carry;
wire sum;
faa f1(carry,sum,a,b,c);
initial begin
a=1'b0;b=1'b0;c=1'b0;
#75 a=1'b0;b=1'b0;c=1'b1;
#75 a=1'b0;b=1'b1;c=1'b0;
#75 a=1'b0;b=1'b1;c=1'b1;
#75 a=1'b1;b=1'b0;c=1'b0;
#75 a=1'b1;b=1'b0;c=1'b1;
#75 a=1'b1;b=1'b1;c=1'b0;
#75 a=1'b1;b=1'b1;c=1'b1;
end
initial
$display($time,"carry=%b,sum=%b,a=%bb=%b,c=%b",carry,sum,a,b,c);

endmodule

Arithmetic circuits Full adder using Gates

FULL ADDER GATE LEVEL MODEL

module favj(a,b,c,sum,carry);
output sum,carry;
input a,b,c;
wire w1,w2,w3;
xor x1(sum,a,b,c);
and a1(w1,a,b);
and a2(w2,b,c);
and a3(w3,c,a);
or o1(carry,w1,w2,w3);
endmodule

Arithmetic circuits-Full Adder Data Flow model

FULL ADDER – DATA FLOW MODEL

module fadfvj(sum,carry,a,b,c);
output sum,carry;
input a,b,c;
assign sum=a^b^c;
assign carry=(a&b)||(b&c)||(a&c);

endmodule