Combinational circuits- Mux8to1 by mux2to1 and testbench

MUX 8 TO 1 USING MUX2TO1 AND ITS TESTBENCH

MUX 2 TO 1
module mux2to1(out,s,a,b);
output out;
input s,a,b;
wire w1,w2,w3;
not n1(w1,s);
and a1(w2,w1,a);
and a2(w3,s,b);
or o1(out,w2,w3);
endmodule

MUX 4 TO 1
module mux4(out,s1,s0,a,b,c,d);
output out;
input s1,s0;
input a,b,c,d;
wire w1,w2;
mux2to1 m1(w1,s0,a,b);
mux2to1 m2(w2,s0,c,d);
mux2to1 m3(out,s1,w1,w2);

endmodule

MUX 8 TO 1
module mux8(out,s2,s1,s0,a,b,c,d,e,f,g,h);
output out;
input s2,s1,s0;
input a,b,c,d,e,f,g,h;
wire w1,w2;
mux4 m1(w1,s1,s0,a,b,c,d);
mux4 m2(w2,s1,s0,e,f,g,h);
mux2to1 m3(out,s2,w1,w2);
endmodule

MUX 8 TO 1 TEST BENCH
module mux8tst;
reg a,b,c,d,e,f,g,h;
reg s2,s1,s0;
wire out;;
mux8 m1(out,s2,s1,s0,a,b,c,d,e,f,g,h);
initial
begin
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
s2=0;s1=0;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=0;s1=0;s0=1;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=0;s1=1;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=0;s1=1;s0=1;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=0;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=0;s0=1;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=1;s0=0;
a=1;b=0;c=1;d=0;e=1;f=0;g=1;h=0;
#75 s2=1;s1=1;s0=1;
end

endmodule