Flipflops and Latches- D Flipflop testbench

D FLIPFLOP TEST BENCH
D FLIPFLOP
module dff(q,clk,d);
output q;
input clk,d;
reg q;
initial
q<=0;
always @(posedge clk)
begin
q<=d;
end
endmodule

TEST BENCH
module dfftest1;
reg clk,d;
wire q;
dff f1(q,clk,d);
initial
begin
clk=0;
d=0;
end
always #75 clk=~clk;
always #150 d=~d;
endmodule