Saturday 4 July 2015

Counters- MOD10 Up counter

MOD 10 UP COUNTER
module mod10bit2(out,rst,clk);
output [3:0]out;
input clk,rst;
reg [3:0]out;
always @(posedge clk)
begin
if(rst|out==4'b1001)
out<=4'b0000;
else
out<=out+1;
end
endmodule

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