Saturday 4 July 2015

Arithmetic circuits- 8bit Accumulator Testbench


8 BIT ACCUMULATOR TEST BENCH

8 BIT ACCUMULATOR
module acc8bit(out,clk,in);
output [7:0]out;
input [7:0]in;
input clk;
reg [7:0]out;
initial
out=8'b0;
always @(posedge clk)
begin
out<=out+in;
end
endmodule

ACCUMULATOR TEST BENCH
module acctest;
reg clk;
reg [7:0]in;
wire [7:0]out;
acc8bit a1(out,clk,in);
initial
begin
clk=1;
in=8'b00000001;
end
always #10 clk=~clk;

endmodule

3 comments:

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  2. "Implementation of 8-bit accumulator using NEXYS-4 ARTIX-7 FPGA board and show the results using seven segment display
    " Verilog code plz

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