Counters- Updown counter 4bit testbench

4 BIT UPDOWN COUNTER TESTBENCH
UP DOWN COUNTER
module updowncounter(q,clk,rst,up);
output [3:0]q;
input clk,rst,up;
reg [3:0]q;
always @(posedge clk)
begin

if(up==1)
begin
if(rst|q==4'b1111)
q<=4'b0000;
else
q<=q+4'b1;
end
else
begin
if(rst|q==4'b0000)
q<=4'b1111;
else
q<=q-1;
end

end

endmodule

TEST BENCH
module updowntest;
reg clk,rst,up;
wire [3:0]q;
updowncounter c1(q,clk,rst,up);
initial
begin
rst=1;
up=0;
clk=1;
end
always #5 clk=~clk;
always #80 rst=~rst;
always #160 up=~up;

endmodule