Flipflops and Latches- T Flipflop testbench

T FLIPFLOP TEST BENCH
T FLIPFLOP
module tff(q,clk,d,t);
output q;
input clk,d,t;
reg q;
initial
q=0;
always @(posedge clk)
begin
if(t)
q<=~d;
else
q<=d;
end
endmodule

TEST BENCH
module tfftest;
reg d,clk,t;
wire q;
tff t2(q,clk,d,t);
initial
begin
clk=0;
d=0;
t=0;
end
always #50 clk=~clk;
always #100 d=~d;
always #200 t=~t;

endmodule