Combinational circuits-Demux1of8 testbench

DEMUX 1 OF 8 TEST BENCH
DEMUX
module demux1of8(d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0,d);
output d0,d1,d2,d3,d4,d5,d6,d7;
input s2,s1,s0,d;
wire w2,w1,w0;
not n1(w2,s2);
not n2(w1,s1);
not n3(w0,s0);
and a1(d0,w2,w1,w0,d);
and a2(d1,w2,w1,s0,d);
and a3(d2,w2,s1,w0,d);
and a4(d3,w2,s1,s0,d);
and a5(d4,s2,w1,w0,d);
and a6(d5,s2,w1,s0,d);
and a7(d6,s2,s1,w0,d);
and a8(d7,s2,s1,s0,d);

endmodule

TEST BENCH
module test;
reg d;
reg s2,s1,s0;
wire d0,d1,d2,d3,d4,d5,d6,d7;
demux1of8 h1(d0,d1,d2,d3,d4,d5,d6,d7,s2,s1,s0,d);
initial
begin
d=1;
s2=0;s1=0;s0=0;
d=1;
#75 s2=0;s1=0;s0=1;
d=1;
#75 s2=0;s1=1;s0=0;
d=1;
#75 s2=0;s1=1;s0=1;
d=1;
#75 s2=1;s1=0;s0=0;
d=1;
#75 s2=1;s1=0;s0=1;
d=1;
#75 s2=1;s1=1;s0=0;
d=1;
#75 s2=1;s1=1;s0=1;
end
endmodule